Method for performing multi-clock static timing analysis

Details Method for performing multi-clock static timing analysis Method for performing multi-clock static timing analysis

2006-05-16

2006-05-16

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C327S170000, C327S291000

Reexamination Certificate

active

07047508

ABSTRACT:
A method for performing multi-clock static timing analysis to determine whether a timing violation occurs on a logic circuit. A set of clock signals that are expected to cause a logic circuit to be in a worst-case situation if analyzed by using static timing analysis can be selected from a number of possible clock signals by using a simple determination process. The selected set of clock signals are then employed in static timing analysis on the logic circuit to verify whether no timing violation occurs on each signal transmission path of the logic circuit. If not, it indicates that the logic circuit using any selection of the possible clock signals will not cause timing violation thereon. Thus, the static timing analysis can be accomplished efficiently.

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