Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
2006-06-06
2006-06-06
Peikari, B. James (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S129000, C711S170000, C711S172000, C711S173000, C711S209000, C711S003000
Reexamination Certificate
active
07058784
ABSTRACT:
A method for managing the access procedure for large block flash memory by employing a page cache block, so as to reduce the occurrence of swap operation is proposed. At least one block of the nonvolatile memory is used as a page cache block. When a host requests to write a data to storage device, the last page of the data is written into one available page of the page cache block by the controller. A block structure is defined in the controller having a data block for storing original data, a writing block for temporary data storage in the access operation, and a page cache block for storing the last one page data to be written.
REFERENCES:
patent: 2002/0004813 (2002-01-01), Agrawal et al.
patent: 2004/0123039 (2004-06-01), Berks et al.
Jianq Chyun IP Office
Peikari B. James
Solid State System Co. Ltd.
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