Metal gate engineering for surface p-channel devices

Details Metal gate engineering for surface p-channel devices Metal gate engineering for surface p-channel devices

2006-06-20

2006-06-20

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S350000, C257S351000

Reexamination Certificate

active

07064390

ABSTRACT:
A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in the NMOS regions while a high work function W (or CoSix)/Ta5Si3/GOx/Si gate stack is formed in the PMOS regions. The improved process also eliminates the need for a nitrided GOx which is known to degrade gm(transconductance) performance. The materials of the semiconductor devices exhibit improved adhesion characteristics to adjacent materials and low internal stress.

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patent: 5576244 (1996-11-01), Hayashi et al.
patent: 5753557 (1998-05-01), Tseng
patent: 5854115 (1998-12-01), Gardner et al.
patent: 5960319 (1999-09-01), Iwata et al.
patent: 6013546 (2000-01-01), Gardner et al.
“Silicon Processing for the VLSI Era” by Stanley Wolf Ph.D.; vol. 2; Process Integration; Lattice Press (1990); ISBN 0-961672-4-5; pp. 301-304.

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