Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2006-11-28
2006-11-28
Ghebretinsae, Temesghen (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S371000, C375S326000
Reexamination Certificate
active
07142623
ABSTRACT:
An integrated circuit is operable to measure tolerance to jitter in a data stream signal. A Clock And Data Recovery Circuit (“CDR”) thereon recovers a phase of a clock for sampling a data stream signal containing a repeatable known sequence of data values and then samples the data stream signal with the recovered clock phase to obtain data stream sample data. An error rate determination circuit independently generates the repeatable known sequence of data values and compares them with the data stream sample data to determine an associated error rate. A control circuit coupled to the CDR delays the recovered clock phase by a predetermined amount a plurality of times and monitors the error rate after each time it delays the recovered clock phase. In this way, a maximum delayed clock phase is determined, representing a right timing signal margin for which the data stream signal can be sampled.
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Ghebretinsae Temesghen
Neff, Esq. Daryl K.
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