Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-11-14
2006-11-14
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07136965
ABSTRACT:
A microcomputer includes (a) a central processing unit, (b) a bus controller electrically connected to the central processing unit through a first bus, (c) a command cache electrically connected to the central processing unit through a second bus, and to the bus controller through a third bus, and (d) a command memory electrically connected to the second bus through a fourth bus, and storing interruption handling routine therein.
REFERENCES:
patent: 6591318 (2003-07-01), Meyer et al.
patent: 6598137 (2003-07-01), Yaegawa et al.
patent: 6651152 (2003-11-01), Ueki et al.
patent: 54-161856 (1979-12-01), None
patent: 61-837 (1986-01-01), None
patent: 3-33955 (1991-02-01), None
patent: 4-195540 (1992-07-01), None
patent: 5-28040 (1993-02-01), None
patent: 8-161176 (1996-06-01), None
patent: WO 96/36919 (1996-11-01), None
Japanese Office Action dated Mar. 7, 2005 (with partial English translation).
Doan Duc T
McGinn IP Law Group PLLC
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