Method for designing an integrated circuit having multiple...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C703S018000

Reexamination Certificate

active

07000214

ABSTRACT:
A method for designing an integrated circuit having multiple voltage domains, including: (a) generating a logical integrated circuit design from information contained in a high-level design file, the high-level design file defining global connection declarations and voltage domain connection declarations; (b) synthesizing the logical integrated circuit design into a synthesized integrated circuit design based upon the logical integrated circuit design, information in a preferred components file and information in a voltage domain definition file; (c) generating a noise model from the synthesized integrated circuit design based on information in the voltage domain definition file and a design constraint file; and (d) simulating the noise model against constraints in the design constraint file and constraints in a circuit level profile file to determine if the synthesized integrated circuit design meets predetermined noise simulation targets.

REFERENCES:
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patent: 6823293 (2004-11-01), Chen et al.
patent: 2001/0017568 (2001-08-01), Kasa et al.
patent: 2004/0133860 (2004-07-01), Hieter et al.
patent: 2004/0172603 (2004-09-01), Collmeyer et al.
patent: 2005/0010887 (2005-01-01), Bednar et al.
patent: 2005/0065765 (2005-03-01), Visweswariah

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