Semiconductor memory device capable of being mounted on a...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185050, C365S189050

Reexamination Certificate

active

07120056

ABSTRACT:
A flash memory device includes a plurality of data pads to receive data from an adjacent plurality of data pins. A signal generation circuit generates a plurality of selection signals responsive to bit organization and package signals. A buffer circuit buffers the data from the plurality of data pads. An input switch receives the data from the buffer circuit and transmits the data to the data lines responsive to the selection signals. And an output switch provides data to the buffer circuit responsive to the selection signals.

REFERENCES:
patent: 5873112 (1999-02-01), Norman
patent: 6285627 (2001-09-01), Kurihara et al.
patent: 6661710 (2003-12-01), Kwon
patent: 2003-132681 (2003-05-01), None
English language abstract of Japanese Publication No. 2003-132681.

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