Semiconductor memory device with a bypass circuit for...

Details Semiconductor memory device with a bypass circuit for... Semiconductor memory device with a bypass circuit for...

2006-04-25

2006-04-25

Mai, Son (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189020, C365S189030

Reexamination Certificate

active

07035164

ABSTRACT:
A semiconductor memory device comprising a bypass circuit for verifying the characteristics of an internal clock signal is provided. The semiconductor memory device having a bypass circuit for verifying the characteristics of an internal clock signal comprises an output circuit, an input circuit, a first bypass circuit and a second bypass circuit. The output circuit outputs data received from an internal circuit, to an input/output (I/O) interface in synchronism with an output clock signal. The input circuit outputs data received from the I/O interface, to the internal circuit in synchronism with an input clock signal. The first bypass circuit transmits the output clock signal to the I/O interface in response to one of a plurality of control signals. The second bypass circuit transmits the input clock signal to the I/O interface in response to one of the plurality of control signals. When one of the first and second bypass circuits is operating, the output circuit and the input circuit stop operating.

REFERENCES:
patent: 5146427 (1992-09-01), Sasaki et al.
patent: 5523981 (1996-06-01), Yamaguchi et al.
patent: 6456561 (2002-09-01), Maeda
patent: 6545937 (2003-04-01), Pawlowski

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