Method for forming an SOI substrate, vertical transistor and...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation

Reexamination Certificate

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C438S429000, C438S770000

Reexamination Certificate

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07084043

ABSTRACT:
A method for producing a silicon-on-insulator layer structure on a silicon surface with any desired geometry can locally produce the silicon-on-insulator structure. The method includes formation of mesopores in the silicon surface region, oxidation of the mesopore surface to form silicon oxide and rib regions from silicon in single-crystal form; and execution of a selective epitaxy process that that silicon grows on the uncovered rib regions, selectively with respect to the silicon oxide regions. Rib regions remain in place between adjacent mesopores, this step being ended as soon as a predetermined minimum silicon wall thickness of the rib regions is reached, the uncovering of the rib regions, which are arranged at the end remote from the semiconductor substrate between adjacent mesopores. The method can be used to fabricate a vertical transistor and a memory cell having a select transistor of this type.

REFERENCES:
patent: 4914628 (1990-04-01), Nishimura
patent: 5177576 (1993-01-01), Kimura et al.
patent: 5256588 (1993-10-01), Witek et al.
patent: 5365097 (1994-11-01), Kenney
patent: 5641694 (1997-06-01), Kenney
patent: 6127246 (2000-10-01), Fukuda
patent: 6262448 (2001-07-01), Enders et al.
patent: 6559069 (2003-05-01), Goldbach et al.
patent: 6949444 (2005-09-01), Torres et al.
patent: 2003/0201479 (2003-10-01), Birner et al.
patent: 0501119 (1992-09-01), None
patent: 0996145 (2000-04-01), None
patent: 1009024 (2000-06-01), None
patent: WO 99/25026 (1999-05-01), None
patent: WO 02/073663 (2002-09-01), None
patent: WO 03/0101826 (2003-02-01), None
V. Lehmann et al., “On the Morphology and the Electrochemical Formation Mechanism of Mesoporous Silicon”. Materials Science and Engineering B69 70, 2000, pp. 11-22, Elsevier Science S.A., Munich, Germany.

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