Delay optimization designing system and delay optimization...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07028273

ABSTRACT:
A delay optimization designing system and method is disclosed by which reduction of outputting delay and setup time of flip-flops and clock skew can be achieved and sufficient delay optimization can be achieved. A delay optimization designing system for a logic circuit includes a flip-flop selection section for selecting any flip-flop not to be substituted into a latch from within a given logic circuit, a flip-flop searching section for searching any flip-flop having a delay margin from among the flip-flops which are not selected by the flip-flop selection section, and a latch substitution section for substituting any flip-flop searched by the flip-flop searching section into a latch which passes a signal to the output side therethrough faster than the searched flip-flop.

REFERENCES:
patent: 6185720 (2001-02-01), Banik
patent: 6536030 (2003-03-01), Tanaka
patent: 6817001 (2004-11-01), Kudlugi et al.
patent: 2003/0023941 (2003-01-01), Wang et al.
patent: 2004/0046590 (2004-03-01), Singh et al.
patent: 6-290232 (1994-10-01), None
patent: 2000-305962 (2000-11-01), None

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