Semiconductor memory device with improved data retention...

Details Semiconductor memory device with improved data retention... Semiconductor memory device with improved data retention...

2006-05-16

2006-05-16

Yoha, Connie C. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S230060, C365S230030, C365S189090

Reexamination Certificate

active

07046543

ABSTRACT:
Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

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K. Fujishima, et al “A Storage-Node-Boosted RAM with Word-Line Delay Compensation” IEEE Journal of Solid-State Circuits, vol., SC-17, No. 5, Oct. 1982, pp. 872-876. U.S. Appl. No. 09/760,804, Filed Jan. 17, 2001.

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