Forming a retrograde well in a transistor to enhance...

Details Forming a retrograde well in a transistor to enhance... Forming a retrograde well in a transistor to enhance...

2006-06-13

2006-06-13

Wilczewski, Mary (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S655000, C257SE29053, C438S289000

Reexamination Certificate

active

07061058

ABSTRACT:
A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

REFERENCES:
patent: 5681771 (1997-10-01), Hwang
patent: 5750435 (1998-05-01), Pan
patent: 5972783 (1999-10-01), Arai et al.
patent: 6143632 (2000-11-01), Ishida et al.
patent: 6162710 (2000-12-01), Ito et al.
patent: 6221705 (2001-04-01), Rost et al.
patent: 6426279 (2002-07-01), Huster et al.
patent: 6603179 (2003-08-01), Ando et al.
patent: 6756279 (2004-06-01), Menut et al.
patent: 6797555 (2004-09-01), Hopper et al.
patent: 2001/0009292 (2001-07-01), Nishinohara et al.
patent: 2001/0016389 (2001-08-01), Wang et al.
patent: 2002/0027243 (2002-03-01), Wu et al.
patent: 2002/0031883 (2002-03-01), Sayama
patent: 2005/0059228 (2005-03-01), Bu et al.
patent: 2005/0118770 (2005-06-01), Nandakumar et al.
patent: 2005/0164431 (2005-07-01), Bu et al.
Scott Thompson, “MOS Scaling: Transistor Challenges for the 21stCentury—Abstract,” Intel Technologies Journal, 3rdQuarter 1998, pp. 1-2.
Scott Thompson, “MOS Scaling: Transistor Challenges for the 21stCentury—Oxide Scaling,” Intel Technologies Journal, 3rdQuarter 1998, pp. 1-9.
Scott Thompson, “MOS Scaling: Transistor Challenges for the 21stCentury—Source Drain Engineering,” Intel Technologies Journal, 3rdQuarter 1998, pp. 1-10.
Scott Thompson, “MOS Scaling: Transistor Challenges for the 21stCentury—Channel Engineering,” Intel Technologies Journal, 3rdQuarter 1998, pp. 1-11.
Scott Thompson, “Mos Scaling: Transistor Challenges for the 21stCentury—Circuit and Device Interactions,” Intel Technologies Journal, 3rdQuarter 1998, pp. 1-6.
Scott Thompson, “MOS Scaling: Transistor Challenges for the 21stCentury—Alternate Device Options,” Intel Technologies Journal, 3rdQuarter 1998, pp. 1-5.
Scott Thompson, “MOS Scaling: Transistor Challenges for the 21stCentury—Conclusion,” Intel Technologies Journal, 3rdQuarter 1998, pp. 1.

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