Shared memory architecture

Details Shared memory architecture Shared memory architecture

2006-10-24

2006-10-24

McLean-Mayo, Kimberly (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S150000, C711S154000, C711S149000, C710S022000

Reexamination Certificate

active

07127563

ABSTRACT:
A wireless communications architecture having first and second synchronous memory devices coupled to a virtual channel memory controller by corresponding first and second data buses, and a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices. The first and second synchronous memory devices are addressed with the shared address bus, and the first and second memory locations are accessed via the first and second data buses, respectively.

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patent: 2001/0053069 (2001-12-01), Haba et al.
patent: 2002/0174311 (2002-11-01), Ware et al.
patent: 2003/0105906 (2003-06-01), Zhao

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