Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2006-03-21

2006-03-21

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S320000, C257S321000, C257S324000, C257S326000

Reexamination Certificate

active

07015540

ABSTRACT:
To realize a semiconductor memory device with reduced cell-to-cell variation in writing characteristics a semiconductor memory has a source region and a drain region, which are formed parallel to each other, and an assist electrode which is between and parallel to the source and drain regions without overlapping, so that at the time of writing, the assist electrode is used as an assist electrode for hot electrons to be injected at the source side and at the time of reading, an inversion layer formed under the assist electrode is used as the source region or the drain region.

REFERENCES:
patent: 6888755 (2005-05-01), Harari
patent: 2004/0079988 (2004-04-01), Harari
patent: 2001-156275 (2001-06-01), None
Arai, et al., “High-Density (4.4F2) NAND Flash Technology UsingSuper-ShallowChannelProfile (SSCP) Engineering,” IEEE International Electron Devices Meeting 2000, pp. 775-778.
Kobayashi, et al., “A Giga-Scale Assist-Gate (AG)—(AND)-Type Flash Memory Cell with 20-MB/s Programming Throughput for Content-Downloading Applications,” IEEE International Electron Devices Meeting 2001 pp. 29-32.
Eitan, et al., “Can NROM, a 2 Bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” International Conference on Solid State Devices and Materials 1999, pp. 522-524.

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