Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-07-18
2006-07-18
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07080349
ABSTRACT:
A method for developing an optimized layout fragmentation script for an optical proximity correction (OPC) simulation tool. A test pattern layout having at least one structure representing a portion of the integrated circuit layout is provided. Optical proximity correction is iteratively conducted on the test pattern layout for each desired permutation of at least one fragmentation parameter associated with the test pattern layout and, for each permutation, a corrected test pattern layout is generated. A printed simulation of each corrected test pattern layout is made and analyzed to select one of the permutations of the at least one fragmentation parameter to apply to a integrated circuit layout prior to correction with the OPC simulation tool.
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Babcock Carl
Capodieci Luigi
Advanced Micro Devices , Inc.
Chiang Jack
Doan Nghia M.
Renner , Otto, Boisselle & Sklar, LLP
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