Method for effectively embedding various integrated circuits...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C714S733000

Reexamination Certificate

active

07082591

ABSTRACT:
A chip stack includes a field programmable gate array (FPGA) and an auxiliary component coupled to the FPGA with intercommunicated clock, control and/or data signals. The auxiliary component has a functionality mapped into the FPGA. The pin definition of the FPGA is redefined so that the FPGA and the auxiliary component in combination operate as a modified FPGA. A test circuit is programmed into the FPGA to exercise the auxiliary component to test functionality and timing performance at full speed. The functionality of the auxiliary component mapped into the FPGA is parameterized, such as for the data word width for reading and/or writing data words of different lengths into the auxiliary component in both an aligned and nonaligned manner. A memory interface allows multiple auxiliary circuits to be accessed through the FPGA either together to generate a wider data word or serially to achieve a greater memory depth.

REFERENCES:
patent: 6044481 (2000-03-01), Kornachuk et al.
patent: 6049222 (2000-04-01), Lawman
patent: 6421813 (2002-07-01), Jeddeloh
patent: 6627985 (2003-09-01), Huppenthal et al.
Ouaiss, I, et al., “Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers”, IEEE, Mar. 2001, pp. 650-657.

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