Method and system for low power refresh of dynamic random...

Static information storage and retrieval – Read/write circuit – Data refresh

Reexamination Certificate

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C365S227000, C365S228000, C365S230060, C365S230040, C365S190000

Reexamination Certificate

active

07072237

ABSTRACT:
A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.

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Applicants also wish to make known that an application, U.S. Appl. No. 10/043,680, describing and claiming subject matter that is similar to the subject matter of this application, was filed on Jan. 10, 2002. This related application, which is a divisional of U.S. Appl. No. 09/803,365, filed Mar. 8, 2001, issued as U.S. Patent No. 6449203, as well as any prior art cited therein, may be material to the examination of this application. A copy of this related application as filed is submitted herewith in accordance with 37 C.F.R. § 1.98(d).
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