Circuits and methods for high-capacity asynchronous pipeline...

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor

Reexamination Certificate

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C326S093000, C326S112000

Reexamination Certificate

active

07053665

ABSTRACT:
A latchless dynamic asynchronous digital pipeline circuit provides decoupled control of pull-up and pull-down. Using two decoupled input, a stage is driven through three distinct phases in sequence: evaluate, isolate and precharge. In the isolate phase, a stage holds its outputs stable irrespective of any changes at its inputs. Adjacent pipeline stages are capable of storing distinct data items without spacers.

REFERENCES:
patent: 5329176 (1994-07-01), Miller, Jr. et al.
patent: 6028453 (2000-02-01), Kong
patent: 6320418 (2001-11-01), Fujii et al.
patent: 6356117 (2002-03-01), Sutherland et al.
patent: 6590424 (2003-07-01), Singh et al.
patent: WO 0182053 (2001-11-01), None
patent: WO 0195089 (2001-12-01), None
Appleton S et al: “High Performance Two-Phase Asynchronous Pipelines” IEICE Transactions on Information and Systems, Institute of Electronics Information and Comm. Eng. Tokyo, JP, vol. E80-D, No. 3, Mar. 1, 1997, pp. 287-294, XP000723715 ISSN: 0916-8532 p. 291, right-hand column, paragraph 2 -p. 292, right-hand column, paragraph 4.
Tan Y K et al.: “Self-Time Precharge Latch” Proceedings of the International Symposium on Circuits and Systems. New Orleans, May 1-3, 1990, New York, IEEE, US, vol. 1 Conf. 23, May 1, 1990, pp. 566-569, XP00016689 p. 566, right-hand column, paragraph 2—p. 567, left-hand column, paragraph 2.
Woods J V et al: “Amulet 1: An Asynchronous Arm Microprocessor” IEEE Transactions on Computers, IEEE Inc. New York, US, vol. 46, No. 4, Apr. 1, 2997, pp. 385-398, XP000656015 ISSN: 0018-9340.
A. Doopley and K. Yun. Optimal clocking and enhanced testability for high-performance self-resetting domino properties. In ARVLSI'99, no date.
D. Harris and M. Horowitz. Skew-tolerant domino circuits. IEEE JSSC. 32(11):1702-1711, Nov. 1997.
W. Liu, C.T. Gray, D. Fan, W.J. Farlow, T.A. Hughes, and R.K. Cavin. A 250-MHz wave pipeland adder in 2-.mu.m CMOS. IEEE JSSC, 29(9):1117-1128, Sep. 1994.
C. Molnar, I. Jones, W. Coates, J. Lexau, S. Fairbanks, and I. Sutherland. Two FIFO ring performance experiments. Proceedings of the IEEE, 87(2):297-307, Feb. 1999.
A. Mukherjee. R. Sudhakar, M. Marke-Sadowska, and S. Long. Wave steering in YADDs: a novel non-iterative syntheses and layout technique. In PROC. DAC. 1999, no month.
V. Narayanan, B. Chappell, and B. Fleischer. Static timing analysis for self resetting circuits. In Proc. ICCAD, 1996, no month.
M. Renaudin, B. Ilassan, and A. Guyot. New asynchronous pipeline scheme: Application to the design of a self-time ring divider. IEEE JSSC, 31(7):1001-1013, Jul. 1996.
M. Singh and S. Nowick. High-throughput asynchronous pipelines for fine-grain dynamic datapaths. In Proc. Ind. Symp. Adv. Res. Async. Circ. Syst. (ASYNC), 2000, no month.
C. van Berkel. M. Josephs, and S. Nowick. Scanning the technology: Applications of asynchronous circuits. Proceedings of the IEEE, 87(2):223-233, Feb. 1999.
T. Williams. Self-Times Rings and their Application to Division. PhD thesis, Stanford University, Jun. 1991.
T. Williams and M. Horowitz. A zero-overhead self-timed 160ns 54b CMOS divider. IEEE JSSC,26(11):1651-1661, Nov. 1991.
D. Wong, G. De Micheli, and M. Flynn. Designing high-performance digital circuits using wave-pipeline. IEEE TCAD, 12(1):Jan. 24-26, 1993.
K. Yun, P. Beersel, and J. Arceo. High-performance asynchronous pipeline circuits. In Proc. Intl. Symp. Adv. Res. Async. Circ. Syst. (ASYNC), 1996, no month.
International Application Ser. No. PCT/US01/13226, International Search Report, Nov. 14, 2001.

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