Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-01-02
1998-08-25
Nguyen, Tuan H.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438639, 438598, 438455, H01L 214763
Patent
active
057982970
DESCRIPTION:
BRIEF SUMMARY
SUMMARY OF THE INVENTION
The present invention relates to semiconductor components having a special structure for electrical connection which allows a high integration density of functional elements on a chip.
For complex CMOS circuits, a positive supply voltage and a negative supply voltage (VDD and VSS) must be fed in, and a multiplicity of signal lines must be routed between the individual transistors. For this purpose, a plurality of wiring planes, i.e. layer-type portions having interconnections and metallizations, must be used, which contain, for example, aluminum interconnections which are insulated from one another by a dielectric such as, for example, SiO2. Connections between these individual planes of interconnections and contacts or from the bottom plane to the transistors and other functional elements on the chip are produced by metal contacts. These contacts are essentially metal-filled holes in the dielectric. With increasing circuit complexity, an ever-increasing number of independent planes with interconnections is necessary in order to provide the requisite electrical connections in sufficient density. As the number of planes increases, the requirement for planarity of the respective dielectric intermediate layers increases, since if the individual layers are insufficiently planarized, production of the next interconnection plane gives rise to technological difficulties. The minimum achievable dimensions of the individual structures consequently increase drastically toward the upper planes. The so-called packing density that can be achieved is thereby considerably reduced. Small capacitances between the signal lines are furthermore necessary for high operating speeds. Supply lines to the external electrical connection terminal should have the lowest possible input line resistances and a high current-carrying capacity. In this case, high capacitances are more beneficial, since these capacitances act as charge stores and can block current spikes.
BACKGROUND OF THE INVENTION
The object of the present invention is to specify a design for a semiconductor component, in which the complexity of the electrical connections is reduced for large-scale integration of the functional elements.
In general terms the present invention is a method for producing a semiconductor component having at least one buried full-area metal layer which is provided with a connection terminal for external power supply, and having active functional elements in a silicon layer. In a first step, a layer structure consisting of each buried full-area metal area and this silicon layer for these active functional elements is produced on a substrate. Dielectric layers for electrical insulation are in each case applied between these layers. In a second step, these active functional elements are produced. In a third step, openings which in each case extend such that a region, intended for making contact, of a functional element is exposed in each opening. In a fourth step, a dielectric is applied onto the wall of these openings up to a height provided for electrical insulation. This region provided for making contact remains exposed in each case. In a fifth step, these openings are filled with metal in order to produce vertical electrically conductive connections between the respective metal layer and this region, provided for making contact, of the functional element.
Advantageous developments of the present invention are as follows.
The fourth step is carried out by depositing the dielectric into the openings, etching away the dielectric anisotropically outside and on the bottom of the openings, filling the openings with a material that resists the etching, in each case up to the height up to which the dielectric is intended to remain, removing the portion of dielectric thereby remaining exposed and removing the material that resists this etching.
In the first step, each buried full-area metal layer is produced from a silicide of a metal from the group titanium, tungsten and tantalum.
The first step is carried out by, in a f
REFERENCES:
patent: 4847732 (1989-07-01), Stopper et al.
patent: 5023205 (1991-06-01), Reche
patent: 5422303 (1995-06-01), Klose et al.
Patent Abstracts of Japan: vol. 17, No. 9, 18 Jan. 1993, JP 04 240 763 dated 28 Aug. 1992.
"Future Packaging Depends Heavily on Materials", by David Maliniak, Electronic Design, Jan. 9, 1992, pp. 83-97.
Alsmeier Johann
Winnerl Josef
Nguyen Tuan H.
Siemens Aktiengesellschaft
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