Semiconductor device having memory and logic devices with...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S296000, C257S306000, C257S309000, C257SE29226

Reexamination Certificate

active

07078758

ABSTRACT:
A semiconductor technique is provided which can achieve both of lowered resistance in a logic formation region and reduced leakage current of the capacitor of a memory device. Source/drain regions (4) are formed in the upper surface of a semiconductor substrate (1) in a memory formation region and cobalt silicide films (9) are formed in the upper surfaces of the source/drain regions (4). Source/drain regions (54) are formed in the upper surface of the semiconductor substrate (1) in a logic formation region and cobalt silicide films (59) are formed in the upper surfaces of the source/drain regions (54). The cobalt silicide films (59) in the logic formation region are thicker than the cobalt silicide films (9) in the memory formation region.

REFERENCES:
patent: 6815281 (2004-11-01), Inoue et al.
patent: 8-31769 (1996-02-01), None
patent: 2000-269482 (2000-09-01), None
patent: 2001-127270 (2001-05-01), None
patent: 2003142608 (2003-05-01), None
patent: WO 98/42009 (1998-09-01), None

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