Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2006-03-21
2006-03-21
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C712S300000
Reexamination Certificate
active
07015718
ABSTRACT:
A method and apparatus for computing flush masks in a multi-threaded processing system provides fast and low-logic-overhead computation of a flush result in response to multiple flush request sources. A flush mask register file is implemented by multiple cells in an array where cells are absent from the diagonal where the column index is equal to the row index. Each cell has a vertical write enable and a horizontal write enable. When a row is written to validate that row's tag value, the is column having an index equal to the row selector is automatically reset (excepting the bit corresponding to the absent cell mentioned above). On a read of a row in the array, a wired-AND circuit provided at each column provides a bit field corresponding to other rows that have been written since a last reset of the row, which is a flush mask indicating newer tags and the selected tag. Each cell in the array has an output for each thread supported by the array, and the logic provides a flush mask output for each thread as well as a combined flush mask output that supports simultaneous access for all of the threads.
REFERENCES:
patent: 5896326 (1999-04-01), Akashi
U.S. Appl. No. 09/687,078, Le, et al.
Burky William Elton
Klim Peter Juergen
Chang Daniel D.
Harris Andrew M.
International Buisness Machines Corporation
Salys Casimer K.
Weiss, Moy & Harris P.C.
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