Circuit and method for reducing SRAM standby power

Details Circuit and method for reducing SRAM standby power Circuit and method for reducing SRAM standby power

2006-01-24

2006-01-24

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Powering

Conservation of power

C365S233100

Reexamination Certificate

active

06990035

ABSTRACT:
A method of operating a memory circuit to reduce standby current is disclosed. The method includes applying a first voltage (Vdd) to a power terminal (224) of a memory cell having a first (612) and a second (614) data terminal. A data bit is stored in a memory cell (600,602,604,606). A second voltage (VDA) different from the first voltage is applied to the power terminal. A third voltage (Ground) is applied to the first and second data terminals. The first voltage is applied to the power terminal.

REFERENCES:
patent: 5873112 (1999-02-01), Norman
patent: 5896318 (1999-04-01), Asada et al.
patent: 6151262 (2000-11-01), Haroun et al.
patent: 6549453 (2003-04-01), Wong

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