Semiconductor memory device adaptive for use circumstance

Details Semiconductor memory device adaptive for use circumstance Semiconductor memory device adaptive for use circumstance

2006-01-03

2006-01-03

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230060

Reexamination Certificate

active

06982923

ABSTRACT:
In a semiconductor memory device, a plurality of memory cell arrays, and each of them includes a plurality of memory cells in a matrix. A mode control unit outputs a delay control signal, and an instruction execution unit accesses to the plurality of memory cells based on an address and an address buffer control signal supplied externally. A command control unit outputs the address buffer control signal to the instruction execution unit based on a command supplied externally and the delay control signal. The command control unit outputs the address buffer signal in synchronization with a clock signal when the delay control signal is in an inactive state and the command is a write command or a read command in an ordinary operation mode. When the delay control signal is in an active state and the command is the write command in a write instruction delay operation mode, also when the delay control signal is in the active state and the command is the read command in a read instruction delay operation mode.

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