Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2006-05-30
2006-05-30
Treat, William M. (Department: 2181)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S243000
Reexamination Certificate
active
07055022
ABSTRACT:
A microprocessor apparatus is provided for performing an indirect near jump operation that includes paired operation translation logic, load logic, and execution logic. The paired operation translation logic receives an indirect near jump macro instruction, and generates a load-jump micro instruction, where the load-jump micro instruction directs load logic to retrieve an offset and directs the execution logic to generate a target address. The load logic is coupled to the paired operation translation logic and receives the load-jump micro instruction. The load logic retrieves the offset from memory, where the offset indicates a jump destination that is relative to an instruction address corresponding to the indirect near jump macro instruction. The execution logic is coupled to the load logic. The execution logic receives the offset, and employs the instruction address and the offset to generate the target address specifying the jump destination for the near jump operation.
REFERENCES:
patent: 5041968 (1991-08-01), Yamaguchi
patent: 5222244 (1993-06-01), Carbine et al.
patent: 5359718 (1994-10-01), Phillips et al.
patent: 6338136 (2002-01-01), Col et al.
Col Gerard M.
Henry G. Glenn
Parks Terry
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