Arrangement of data within cache lines so that tags are...

Details Arrangement of data within cache lines so that tags are... Arrangement of data within cache lines so that tags are...

2006-04-11

2006-04-11

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S129000, C711S141000, C711S144000, C711S170000, C714S766000, C714S768000, C714S777000

Reexamination Certificate

active

07028150

ABSTRACT:
A memory system and method for processing a data structure comprising a plurality of data bits representing a line of memory, wherein the data bits are divided into a plurality of data chunks, each of the data chunks including at least an error correction code portion and a data portion; and a first chunk of said plurality of data chunks having a tag portion, wherein said tag portion includes tag information for the entire line of memory, and wherein subsequent ones of said data chunks do not include tag information.

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