Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Bad bit

Reexamination Certificate

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C365S230060, C365S230080

Reexamination Certificate

active

06982912

ABSTRACT:
The semiconductor memory device comprises a plurality of word lines including one or more redundant word lines; a plurality of pairs of bit lines; a plurality of memory cells connected to the above-mentioned plurality of word lines and the above-mentioned plurality of pairs of bit lines; a plurality of word-line drivers, each of which is connected to respective one ends of the above-mentioned plurality of word lines and controlled by a plurality of word-line control signals; and a plurality of first word-line control circuits respectively located at the other ends of the above-mentioned plurality of word lines, each of the above-mentioned plurality of first word-line control circuits receiving a signal level of a corresponding one of the above-mentioned plurality of word lines.

REFERENCES:
patent: 5889711 (1999-03-01), Yang et al.
patent: 6762971 (2004-07-01), Yamagami
patent: 11-213690 (1999-08-01), None

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