Method and circuit for error correction in CAM cells

Details Method and circuit for error correction in CAM cells Method and circuit for error correction in CAM cells

2006-03-07

2006-03-07

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

Reexamination Certificate

active

07010741

ABSTRACT:
A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array. The method includes the following steps: a row parity bit corresponding to a parity of a first plurality of bits stored along a row of CAM cells is stored; a column parity bit corresponding to the parity of a second plurality of bits stored along a column of CAM cells is stored; a parity of the first plurality of bits is read and generated and the generated parity is compared to the stored row parity bit; if the generated and stored parity bits do not match, columns of the array are cycled through; a parity of the second plurality of bits is read and generated and the generated parity is compared to the stored column parity bit until a mismatch is indicated; and, a bit located at an intersection of the mismatched row and column is inverted if the mismatch is indicated.

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Pinaki Mazumder, “An On-Chip ECC Circuit for Correcting Soft Errors in DRAM's with Trench Capacitors”, IEEE JSSC, vol. 27, No. 11, Nov. 1992.

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