Methods of forming a conductive line

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S435000, C438S620000, C438S668000

Reexamination Certificate

active

07081398

ABSTRACT:
A method of forming a local interconnect includes forming an isolation trench within a semiconductor substrate. A first trench isolation material is deposited to within the trench. First isolation material is removed effective to form a line trench into a desired local interconnect. Conductive material is formed therewithin. A second isolation material is deposited over the first isolation material, over the conductive material within the isolation trench and within the line trench. At least some first and second isolation material is removed in at least one common removing step. Integrated circuitry includes a substrate comprising trench isolation material. A local interconnect line is received within a trench formed within the isolation material. The local interconnect includes at least two different conductive materials. One of the conductive materials lines the trench. Another of the conductive materials is received within a conductive trench formed by the one. Other implementations are disclosed.

REFERENCES:
patent: 4661202 (1987-04-01), Ochii
patent: 5573969 (1996-11-01), Kim
patent: 5614765 (1997-03-01), Avanzino et al.
patent: 5920098 (1999-07-01), Liaw
patent: 5970375 (1999-10-01), Gardner et al.
patent: 6008084 (1999-12-01), Sung
patent: 6011712 (2000-01-01), Lee
patent: 6017813 (2000-01-01), Kuo
patent: 6027994 (2000-02-01), Huang et al.
patent: 6071804 (2000-06-01), Gau
patent: 6133116 (2000-10-01), Kim et al.
patent: 6180494 (2001-01-01), Manning
patent: 6258709 (2001-07-01), McDaniel
patent: 6271125 (2001-08-01), Yoo et al.
patent: 6287965 (2001-09-01), Kang et al.
patent: 6337274 (2002-01-01), Hu et al.
patent: 6346438 (2002-02-01), Yagishita et al.
patent: 6350679 (2002-02-01), McDaniel et al.
patent: 6365504 (2002-04-01), Chien et al.
patent: 6376380 (2002-04-01), Tang et al.
patent: 6394883 (2002-05-01), Carlson et al.
patent: 6461225 (2002-10-01), Misra et al.
patent: 6498088 (2002-12-01), Trivedi
patent: 6720269 (2004-04-01), Park et al.
patent: 6724054 (2004-04-01), Kang et al.
patent: 6730570 (2004-05-01), Shin et al.
patent: 2001/0003663 (2001-06-01), Huang
patent: 2002/0072224 (2002-06-01), Huang et al.
patent: 0457131 (1991-11-01), None
Wolf et al [“Silicon Processing For the VLSI ERA”, vol. 1 Process technology, pp. 5-6, Lattic Press 1986].
U.S. Appl. No. 10/925,158, filed Aug. 2004, Southwick et al.

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