Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-01-17
2006-01-17
Zarneke, David (Department: 2891)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S681000, C438S763000, C438S785000, C438S240000, C438S625000, C438S677000, C438S783000, C438S754000, C171S093000, C171S084000, C171S089000, C427S248100, C427S252000, C427S255310, C427S255360, C427S343000
Reexamination Certificate
active
06987063
ABSTRACT:
A metal-containing semiconductor layer having a high dielectric constant is formed with a method that avoids inclusion of contaminant elements that reduce dielectric constant of metals. The metal-containing semiconductor layer is formed overlying a substrate in a chamber. A precursor is introduced to deposit at least a portion of the metal-containing semiconductor layer. The precursor contains one or more elements that, if allowed to deposit in the metal-containing layer, would become impurity elements. A reactant gas is used to purify the metal-containing layer by removing impurity elements from the metal-containing layer which were introduced into the chamber by the precursor.
REFERENCES:
patent: 6200893 (2001-03-01), Sneh
patent: 6270572 (2001-08-01), Kim et al.
patent: 6468924 (2002-10-01), Lee et al.
patent: 6576053 (2003-06-01), Kim et al.
patent: 6869638 (2005-03-01), Baum et al.
patent: 2003/0003230 (2003-01-01), Kim et al.
patent: 2003/0234417 (2003-12-01), Raaijmakers et al.
patent: 2004/0043557 (2004-03-01), Haukka et al.
patent: 2004/0168627 (2004-09-01), Conley et al.
patent: 2004/0261692 (2004-12-01), Dwilinski et al.
patent: 2005/0012089 (2005-01-01), Senzaki et al.
patent: 2005/0070126 (2005-03-01), Senzaki
patent: WO 2004/008827 (2004-01-01), None
patent: WO 2004/017377 (2004-02-01), None
patent: WO 2004/041753 (2004-05-01), None
Nigro, Raffaella Lo et al.; “Fabrication of LaAlO3/Pt(100)/Hastelloy C276 and CeO2(100)/Pt(100)Hastelloy C276 Multilayers by Metallorganic Chemical Vapor Deposition”, Journal of The Electrochemical Society; Jun. 29, 2001; pp F159-F163; vol. 148 (8).
Gordon, Roy G. et al.; “Alternating Layer Chemical Vapor Deposition (ALD) of Metal Silicates and Oxides for Gate Insulators”; Mat. Res. Soc. Symp. Proc.; 2001; pp 2.4.1-2.4.6; vol. 670.
Innertsberger, G. e al.; “The Influence of Flourine on Various MOS Devices”; Mat. Res. Soc. Symp. Proc.; 1999; pp 589-595; vol. 567.
Ritala, Mikko et al.; “Atomic Layer Deposition”; Handbook of Thin Film Materials, Chapter 2; 2002; pp 103-159; vol. 1: Deposition and Processing of Thin Films; Academic Press.
Adetutu Olubunmi O.
Schaeffer James K.
Triyoso Dina H.
Chiu Joanna G.
King Robert L.
Yevsikov Victor V.
Zarneke David
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