Series connected TC unit type ferroelectric RAM and test...

Details Series connected TC unit type ferroelectric RAM and test... Series connected TC unit type ferroelectric RAM and test...

2006-01-31

2006-01-31

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S145000

Reexamination Certificate

active

06993691

ABSTRACT:
Potential of a word line connected to any selected one of memory cells is lowered and potential of word lines connected to non-selected memory cells are raised. The potential of the plate line is raised and lowered. The potential of the bit line is raised and lowered. After this, reading data from the memory cells after potential raising and lowering of the plate line and potential raising and lowering of the bit line have been alternately performed at least one time, thereby to determine attenuation of polarization in the ferroelectric capacitor.

REFERENCES:
patent: 5903492 (1999-05-01), Takashima
patent: 6301145 (2001-10-01), Nishihara
patent: 6658608 (2003-12-01), Kamp et al.
D. Takashima, et al., “High Density Chain Ferroelectric Random-Access Memory (CFRAM)”, VLSI Circuit Symposium, 1997, p. 83-84.
D. Takashima, et al., “A Sub-40ns Random-Access Chain FRAM Architecture with a 7ns Cell-Plate-Line Drive”, ISSCC Digest of Technical Papers, Feb. 1999, p. 102-103.

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