Semiconductor memory device inputting/outputting data and...

Details Semiconductor memory device inputting/outputting data and... Semiconductor memory device inputting/outputting data and...

Filed on

2006-07-11

Date issued

2006-07-11

Examiner

Dinh, Son T. (Department: 2824)

Patent Class

Static information storage and retrieval

SubClass

Addressing

SubSubClass

Particular decoder or driver circuit

Other Related Categories

C365S233100

Type

Reexamination Certificate

Status

active

Patent number

07075851

Description

ABSTRACT:
A control circuit controls a column decoder and a parity column decoder such that parity data is input/output to a memory cell array at a timing different from that of input/output of data corresponding to the parity data to/from the memory cell array. Therefore, a terminal for parity data input/output is not necessary, and a memory device can be adapted to an ECC function without increasing a memory bus width.

REFERENCES:
patent: 5002031 (1991-03-01), Kako
patent: 5604703 (1997-02-01), Nagashima
patent: 5905673 (1999-05-01), Khan
patent: 6269048 (2001-07-01), Kano et al.
patent: 6510537 (2003-01-01), Lee
patent: 6717879 (2004-04-01), Tanaka
patent: 11-65944 (1999-03-01), None
patent: 479170 (2002-03-01), None

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