Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-07-18
2006-07-18
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S776000
Reexamination Certificate
active
07080309
ABSTRACT:
A method and an apparatus are used to maximize available transmission bandwidth by using multiple error correcting code (ECC) schemes. A transaction between components in a computer system may involve the transmission of header information in a header packet. One or more separate data packets may then be used to transmit other data, depending on the particular transaction and the transmission bandwidth. Using a multiple ECC scheme, the header packet and transactions with a small number of data packets may be protected using one type of ECC. The data packets part of a large transaction with a large number of data packets may be protected by another compact ECC, thus significantly reducing the ECC overhead, and improving transmission bandwidth. To reduce data latency, parity bits may be distributed with each of the data packets, with the remaining ECC bits included in the last data packet. Alternatively, an ECC may be used where the parity bits for data bits in a packet are with their respective data packets and the remaining ECC bits are sent on one or more data packets. This arrangement allows early detection of single bit errors in a specific data packet, and thus reduces latency.
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