Memory technology test apparatus

Details Memory technology test apparatus Memory technology test apparatus

2006-03-28

2006-03-28

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S738000

Reexamination Certificate

active

07020815

ABSTRACT:
A programmable control device that creates an environment for controlling, testing and evaluating memory designs. The control device provides automated testing of address eyes, data eyes and voltage margins. The control device interfaces with a conventional computer system, such as a personal computer (PC). The computer system gathers test data and outputs the data in a graphical format if desired. Since the control device is quickly re-programmable, new memory sequencing, control, timing and power techniques are rapidly proto-typed in an inexpensive and timely manner.

REFERENCES:
patent: 5513315 (1996-04-01), Tierney et al.
patent: 5673271 (1997-09-01), Ohsawa
patent: 6285962 (2001-09-01), Hunter
patent: 6567941 (2003-05-01), Turnquist et al.
patent: 2002/0046374 (2002-04-01), Aoki et al.
patent: 2004/0153274 (2004-08-01), Fukuda

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