Methods of plating via interconnects

Details Methods of plating via interconnects Methods of plating via interconnects

2006-09-05

2006-09-05

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S667000, C438S675000, C438S928000

Reexamination Certificate

active

07101792

ABSTRACT:
Methods for filling high aspect ratio vias with conductive material. At least one high aspect ratio via is formed in the backside of a semiconductor substrate. The at least one via is closed at one end by a conductive element forming a conductive structure of the semiconductor substrate. The backside of the semiconductor substrate is exposed to an electroplating solution containing a conductive material in solution with the active surface semiconductor substrate isolated thereform. An electric potential is applied across the conductive element through the electroplating solution and a conductive contact pad in direct or indirect electrical communication with the conductive element at the closed end of the at least one via (or forming such conductive element) to cause conductive material to electrochemically deposit from the electroplating solution and fill the at least one via. Semiconductor devices and in-process semiconductor devices are also disclosed.

REFERENCES:
patent: 4692349 (1987-09-01), Georgiou et al.
patent: 4808273 (1989-02-01), Hua et al.
patent: 4978639 (1990-12-01), Hua et al.
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5897368 (1999-04-01), Cole, Jr. et al.
patent: 6032527 (2000-03-01), Genova et al.
patent: 6169024 (2001-01-01), Hussein
patent: 6197664 (2001-03-01), Lee et al.
patent: 6242935 (2001-06-01), Akram
patent: 6255126 (2001-07-01), Mathieu et al.
patent: 6277669 (2001-08-01), Kung et al.
patent: 6291332 (2001-09-01), Yu et al.
patent: 6384481 (2002-05-01), Hussein et al.
patent: 6406939 (2002-06-01), Lin
patent: 6418616 (2002-07-01), Bhatt et al.
patent: 6448644 (2002-09-01), Lin
patent: 6468889 (2002-10-01), Iacoponi et al.
patent: 6562709 (2003-05-01), Lin
patent: 6565729 (2003-05-01), Chen et al.
patent: 2003/0057097 (2003-03-01), Tsai et al.
U.S. Appl. No. 10/379,890, filed Mar. 5, 2003, for “Conductive Through Wafer Vias”.

Affiliated with

Also associated with

Rating

Methods of plating via interconnects does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of plating via interconnects, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of plating via interconnects will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3586262