Semiconductor fabrication process with asymmetrical...

Details Semiconductor fabrication process with asymmetrical... Semiconductor fabrication process with asymmetrical...

2006-09-19

2006-09-19

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S319000, C257S401000, C257S407000, C257SE21626

Reexamination Certificate

active

07109550

ABSTRACT:
A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode116are independently doped such that each of the structures may be n-type or p-type. Source/drain regions (156) are implanted laterally disposed on either side of the spacers (146, 150). Spacers (146, 150) may be independently doped by using a first angled implant (132) to dope first extension spacer (146) and a second angled implant (140) to dope second spacer (150). In one embodiment, the use of differently doped extension spacers (146, 150) eliminates the need for threshold adjustment channel implants.

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