Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2006-05-23
2006-05-23
Peikari, B. James (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S144000
Reexamination Certificate
active
07051166
ABSTRACT:
A memory system employing a directory-based cache coherency scheme comprises a memory unit, a data bus, a plurality of information buses, and a memory controller. The memory unit comprises a plurality of memory modules storing a plurality of cache lines, with each cache line comprising a plurality of data bits and an associated plurality of informational bits. The data bus is coupled to each of the memory modules and is configured to read/write data from/to the memory modules. One information bus of the plurality of information buses is coupled to each of the memory modules and is configured to read/write informational bits to/from the memory modules.
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