Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2006-07-18
2006-07-18
Nguyen, Tuan T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S203000, C365S230080
Reexamination Certificate
active
07079439
ABSTRACT:
A power saving circuit disables input buffers for command and address signals during an auto-refresh of a DRAM. The input buffers are re-enabled at the end of the auto-refresh in a manner that does not cause spurious commands to be generated. The power saving circuit prevents spurious commands by biasing internal command signals to a “no operation” command whenever the input buffers for the command signals are disabled. The DRAM may also be placed in a mode in which it automatically transitions to a low power precharge mode at the end of the auto-refresh to further reduce power consumed by the DRAM.
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Blodgett Greg A.
Cowles Timothy B.
Shirley Brian M.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nguyen Hien
Nguyen Tuan T.
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