MFIS ferroelectric memory array

Details MFIS ferroelectric memory array MFIS ferroelectric memory array

2006-09-26

2006-09-26

Booth, Richard A. (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000

Reexamination Certificate

active

07112837

ABSTRACT:
An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.

REFERENCES:
patent: 6531324 (2003-03-01), Hsu et al.
patent: 6711049 (2004-03-01), Hsu et al.

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