Wafer bonding method of forming silicon-on-insulator...

Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S459000, C438S404000

Reexamination Certificate

active

06984570

ABSTRACT:
A wafer bonding method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing at least a portion of an outer surface of silicon of a device wafer. After the nitridizing, the device wafer is joined with a handle wafer. A method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing an interface of the silicon comprising layer of silicon-on-insulator circuitry with the insulator layer of the silicon-on-insulator circuitry. After the nitridizing, a field effect transistor gate is formed operably proximate the silicon comprising layer. Other methods are disclosed. Integrated circuitry is contemplated regardless of the method of fabrication.

REFERENCES:
patent: 5021843 (1991-06-01), Ohmi
patent: 5374329 (1994-12-01), Miyawaki
patent: 5405802 (1995-04-01), Yamagata et al.
patent: 5453394 (1995-09-01), Yonehara et al.
patent: 5670411 (1997-09-01), Yonehara et al.
patent: 5767020 (1998-06-01), Sakaguchi et al.
patent: 5773355 (1998-06-01), Inoue et al.
patent: 5841171 (1998-11-01), Iwamatsu et al.
patent: 5849627 (1998-12-01), Linn et al.
patent: 5882532 (1999-03-01), Field et al.
patent: 5910672 (1999-06-01), Iwamatsu et al.
patent: 6010921 (2000-01-01), Soutome
patent: 6037634 (2000-03-01), Akiyama
patent: 6048411 (2000-04-01), Henley et al.
patent: 6071783 (2000-06-01), Liang et al.
patent: 6091076 (2000-07-01), Deleonibus
patent: 6215155 (2001-04-01), Wollesen
patent: 6245636 (2001-06-01), Maszara
patent: 6255731 (2001-07-01), Ohmi et al.
patent: 6265327 (2001-07-01), Kobayashi et al.
patent: 6268630 (2001-07-01), Schwank et al.
patent: 6313014 (2001-11-01), Sakaguchi et al.
patent: 6340829 (2002-01-01), Hirano et al.
patent: 6245729 (2002-02-01), Maszara
patent: 6346729 (2002-02-01), Liang et al.
patent: 6350703 (2002-02-01), Sakaguchi et al.
patent: 6358791 (2002-03-01), Hsu et al.
patent: 6403485 (2002-06-01), Quek et al.
patent: 6410938 (2002-06-01), Xiang
patent: 6433401 (2002-08-01), Clark et al.
patent: 6509613 (2003-01-01), En et al.
patent: 6512244 (2003-01-01), Ju et al.
patent: 6531375 (2003-03-01), Giewont et al.
patent: 6534380 (2003-03-01), Yamauchi et al.
patent: 6541861 (2003-04-01), Higashi et al.
patent: 6552396 (2003-04-01), Bryant et al.
patent: 6552496 (2003-04-01), Yamazaki
patent: 6610615 (2003-08-01), McFadden et al.
patent: 6642579 (2003-11-01), Fung
patent: 6649959 (2003-11-01), Hsu et al.
patent: 6661065 (2003-12-01), Kunikiyo
patent: 6664146 (2003-12-01), Yu
patent: 6680243 (2004-01-01), Kamath et al.
patent: 2001/0020722 (2001-09-01), Yang
patent: 2002/0011670 (2002-01-01), Higashi et al.
patent: 2002/0034844 (2002-03-01), Hsu et al.
patent: 2002/0048644 (2002-04-01), Sakaguchi
patent: 2002/0048844 (2002-04-01), Sakaguchi
patent: 2002/0070454 (2002-06-01), Yasukawa
patent: 2002/0134503 (2002-09-01), Hussinger et al.
patent: 2003/0085424 (2003-05-01), Bryant et al.
Bernstein et al.,Floating Body Effects, SOI Device Electrical Properties 34-53 (pre-Aug. 2001).
U.S. Appl. No. 10/924,776, filed Aug. 25, 2004, Ford.
Bashir et al.,Characterization of sidewall defects in selective epitaxial growth of silicon, 13 J. Vac. Sci. Technol. B, No. 3, pp. 923-927 (May/Jun. 1995).
Bashir et al.,Reduction of sidewall defect induced leakage currents by the use of nitrided field oxides in silicon selective epitaxial growth . . ., 18 J. Vac. Sci. Technol. B, No. 2, pp. 695-699 (Mar./Apr. 2000).
Hammad et al.,The Pseudo-Two-Dimensional Approach to Model the Drain Section in SOI MOSFETs, 48 IEEE Transactions on Electron Devices, No. 2, pp. 386-387 (Feb. 2001).
Sivagnaname et al.,Stand-by Current in PD-SOI Pseudo-nMOS Circuits, IEEE, pp. 95-96 (2003).
Wang et al.,Achieving Low Junction Capacitance on Bulk SI MOSFET Using SDOI Process, Micron Technology, Inc., 12 pages (pre-2004).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Wafer bonding method of forming silicon-on-insulator... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer bonding method of forming silicon-on-insulator..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer bonding method of forming silicon-on-insulator... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3578984

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.