Mask pattern and method for forming resist pattern using...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07032209

ABSTRACT:
A mask pattern for multiple exposure for forming a resist pattern with an unvarying pattern pitch on a semiconductor wafer, which is utilized as in case where a mask pattern under a design having the width of an aperture pattern smaller than the width of a light-shielding pattern is used at one exposure, wherein the mask pattern for multiple exposure has a pattern pitch that is the same as that of the mask pattern under design and has the width of an aperture pattern greater than the width of a light-shielding pattern.

REFERENCES:
patent: 6047116 (2000-04-01), Murakami et al.
patent: 6701512 (2004-03-01), Sutani et al.
patent: 2001/0036583 (2001-11-01), Hasegawa et al.
patent: 3-201422 (1991-09-01), None
patent: 4-267537 (1992-09-01), None
patent: 4-273427 (1992-09-01), None
patent: 4-355910 (1992-12-01), None

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