Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-04-25
2006-04-25
Le, Thao P. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S421000
Reexamination Certificate
active
07033926
ABSTRACT:
An interconnect arrangement comprises a substrate made from a first insulating material with a substrate surface, at least two interconnects which are arranged next to one another in the substrate, a buffer layer made from a second insulating material above the substrate and comprising a buffer-layer surface, which is parallel to the substrate surface, at least one cavity, which is arranged between the interconnects and, with respect to the buffer-layer surface, extends deeper into the substrate than the interconnects, and a covering layer made from a third insulating material, which is arranged above the buffer layer and completely closes off the cavity with respect to the buffer-layer surface.
REFERENCES:
patent: 5510645 (1996-04-01), Fitch et al.
patent: 5792706 (1998-08-01), Michael et al.
patent: 5908318 (1999-06-01), Wang et al.
patent: 6242336 (2001-06-01), Ueda et al.
patent: 6472266 (2002-10-01), Yu et al.
patent: 6890830 (2005-05-01), Tamaoka et al.
patent: 6914318 (2005-07-01), Lee et al.
patent: 1026726 (2000-08-01), None
Kusuki, T., et al., “Spontaneous Etching of SiO2Employing H2/NF3Downstream Plasma”, Extended Abstracts of the Electrochemical Society, vol. 93, No. 1, pp. 375-376, 1993.
Fleming, J.G., et al. “Lowering of Intralevel Capacitance Using Air Gap Structures,” Conference Proceedings ULSI XII, Materials Research Society, pp. 471-477, 1997.
Shieh, B. et al., “Air-Gap Formation During IMD Deposition to Lower Interconnect Capacitance,” IEEE Electron Device Letters, vol. 19, No. 1, pp. 16-18, 1998.
Shieh, B, et al., “Integration and Reliability Issues for Low Capacitance Air-Gap Interconnect Structures,” IEEE Proc. 1998 IITC, pp. 125-127, 1998.
Ueda, T., et al. “A Novel Air Gap Integration Scheme for Multi-level Interconnects Using Self-aligned Via Plugs,” IEEE Proc. 1998 Symp. VLSI Techn. Digest of Technical Papers, pp. 46-47, 1998.
Shieh, B. et al., “Air Gaps Lower k of Interconnect Dielectrics,” Solid State Technology, pp. 51-58, Feb. 1999.
Ueda, T., et al., “Integration of 3 Level Air Gap Interconnect for Sub-quarter Micron CMOS,” IEEE Proc. 1999 Symp. VLSI Techn. Digest of Technical Papers, 1999.
Arnal, V., et al. “A Novel SiO2-Air Gap Low K for Copper Dual Damascene Interconnect,” Advanced Metallization Conference 2000, pp. 71-76.
Arnal, V., et al., “Integration of a 3 Level Cu-SiO2Air Gap Interconnect for Sub 0.1 micron CMOS Technologies,” IEEE Proc. 2001 IITC, 2001.
Gabric Zvonimir
Pamler Werner
Schindler Günther
Dicke Billig & Czaja, PLLC
Infineon - Technologies AG
Le Thao P.
LandOfFree
Strip conductor arrangement and method for producing a strip... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Strip conductor arrangement and method for producing a strip..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Strip conductor arrangement and method for producing a strip... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3577849