Buffer management in packet switched fabric devices

Details Buffer management in packet switched fabric devices Buffer management in packet switched fabric devices

2006-07-11

2006-07-11

Huynh, Kim (Department: 2182)

Electrical computers and digital data processing systems: input/

Interrupt processing

Interrupt prioritizing

C710S244000, C710S107000, C710S036000, C710S040000, C709S225000, C709S250000

Reexamination Certificate

active

07076587

ABSTRACT:
A buffer management system for cooperating with a packet based switching system is proposed. The purpose of this system is to reduce traffic congestion, ameliorate its effects, provide fairness to each data source, and to increase functionality while respecting advantageous system characteristics. Fabric output buffers include an arbitration function, a quality of service function, and are associated with individual routing tables. The system uses shallow logic that allows for single clock cycle operation even at high clock speeds. In order to provide for system control of bandwidth, sources with bandwidth practices counter to system interests are addressed. Where there is a conflict of sources over a resource, the buffer management system arbitrates traffic to resolve conflicts in a timely manner while fairly allocating traffic share using a weighted round robin arbitration scheme.

REFERENCES:
patent: 5481680 (1996-01-01), Larson et al.
patent: 5797020 (1998-08-01), Bonella et al.
patent: 6035361 (2000-03-01), Kim et al.

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