Register controlled delay locked loop circuit

Details Register controlled delay locked loop circuit Register controlled delay locked loop circuit

2006-09-05

2006-09-05

Tran, Khai (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S375000, C327S158000

Reexamination Certificate

active

07103133

ABSTRACT:
A register controlled delay locked loop (DLL) includes a clock divider, a shift controller, a delay unit and a delay model to synchronize an external clock signal with an internal clock. The register controlled DLL further includes a reset signal generator to generate a reset signal used to initialize the delay locked loop (DLL), a phase comparator to initialize a phase comparison signal in which the phase of a feedback clock signal delayed by a reference clock signal and the delay model is compared and outputted into a predetermined signal by using a comparison enable signal having an inverse phase to that of the reset signal, and a shift register to block an electric current running on a first latch of a plurality of latches with the reset signal during the initialization.

REFERENCES:
patent: 6144713 (2000-11-01), Eto
patent: 6222894 (2001-04-01), Lee
patent: 2002/0105848 (2002-08-01), Tomita et al.
patent: 1998-0069826 (1998-10-01), None
patent: 2000-0011729 (2000-02-01), None
Hatakeyama et al., A 256-Mb SDRAM Using a Regiser-Contolled Digital DLL, IEEE Journal of Solid-State Circuits, vol. 31, No. 11 Nov. 1997.

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