Strained-channel isolated-gate field effect transistor,...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S327000, C257S616000

Reexamination Certificate

active

06989570

ABSTRACT:
A transistor is located on a base layer1resting on a semiconductor substrate SB and formed from a relaxed silicon-germanium layer, and includes, under the isolated gate7, a first strained silicon layer2resting on the base layer1, surmounted by a buried insulating layer10, surmounted by a second strained silicon layer4extending between the source S and drain D regions.

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patent: 6515335 (2003-02-01), Christiansen et al.
patent: 6537894 (2003-03-01), Skotnicki et al.
patent: 6656782 (2003-12-01), Skotnicki et al.
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patent: 09321307 (1997-12-01), None
patent: WO 01/54202 (2001-07-01), None
Skotnicki, et al., “Heavily doped and extremely shallow junctions on insulator— by SONCTION (SilicONCut-off juncTION) process”;Electron Devices Meeting, 1999,IEDM Technical Digest, International Washington, D.C. Dec. 5-8, 1999, Piscataway, New Jersey,IEEE, US , Dec. 5, 1999, pps. 513-516, XP010372064.
Maiti, et al., “Strained-Si heterostructure field effect transistors”,Semiconductor Science and Technology, Institute of Physics, vol. 13, No. 11, London, GB, Nov. 1, 1998, XP000783138.
Thomas Skotnicki, Silicon On Nothing (SON)— Fabrication, Material and Devices,Electrochemcial Society Proceedings, vol. 2001, No. 3, Mar. 25-29, 2001; XP008014133.
Ribot, et al., “Selective SiGe epitaxy by rtcvd for new device architectures”,Materials Science and Engineering B, Elsevier Sequoia, Lausanne, CH, vol. 89, No. 1-3, Feb. 14, 2002, pps. 125-128, XP004334382.
Anonymous, “MOS Transistors with Bottom-Isolated Source/Drain Regions”, research disclosure,Kenneth Mason PublicationsHampshire, GB, No. 398, dated Jun. 1, 1997, pps. 378-379, XP000726504.
French Search Report, FA 621699/FR 0204165, dated Feb. 24, 2003.

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