Semiconductor memory device with reduced power consumption...

Details Semiconductor memory device with reduced power consumption... Semiconductor memory device with reduced power consumption...

2006-01-31

2006-01-31

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189120

Reexamination Certificate

active

06992944

ABSTRACT:
A semiconductor memory device includes a plurality of word decoders arranged in a plurality of columns, a plurality of word line selecting shift registers corresponding to the respective word decoders to indicate a word line subjected to refresh operation, and a shift control signal generating circuit operable to supply a shift control signal indicative of timing of shift operations to the plurality of word line selecting shift registers, wherein the said shift control signal generating circuit is configured to supply the shift control signal only to a column currently subjected to refresh operation among the plurality of columns.

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