Memory wordline spacer

Details Memory wordline spacer Memory wordline spacer

2006-05-30

2006-05-30

Booth, Richard A. (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S954000

Reexamination Certificate

active

07053446

ABSTRACT:
A memory includes a semiconductor substrate and a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited and formed. A doped wordline spacer layer is deposited and a doped wordline spacer is formed adjacent to the wordline.

REFERENCES:
patent: 6248635 (2001-06-01), Foote et al.
patent: 6458661 (2002-10-01), Sung
patent: 6504207 (2003-01-01), Chen et al.

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