Static information storage and retrieval – Read/write circuit – Simultaneous operations
Reexamination Certificate
2006-03-07
2006-03-07
Auduong, Gene N. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Simultaneous operations
C365S189011, C365S185250
Reexamination Certificate
active
07009892
ABSTRACT:
A semiconductor memory device includes a control logic circuit for generating read selection signals each selecting one plane for reading and write selection signals each selecting one plane for writing from a plurality of planes in which memory cells are arranged in an array, an address selection circuit disposed for each of the planes, and an address buffer circuit for simultaneously providing a write address and a read address. Each of the address selection circuits is configured so as to be able to receive one of the read selection signals and one of the write selection signals from the control logic circuit. The memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.
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patent: 5424979 (1995-06-01), Morii
patent: 5509134 (1996-04-01), Fandrich et al.
patent: 6240040 (2001-05-01), Akaogi et al.
patent: 6740927 (2004-05-01), Jeng
patent: 5-304277 (1993-11-01), None
Office Action mailed Jun. 1, 2005 for U.S. Patent Application No. 10/851,709 filed May 20, 2004.
Iwata Hiroshi
Morikawa Yoshinao
Nawaki Masaru
Shibata Akihide
Auduong Gene N.
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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