Non-volatile memory integrated circuit

Details Non-volatile memory integrated circuit Non-volatile memory integrated circuit

2006-01-24

2006-01-24

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S314000

Reexamination Certificate

active

06989562

ABSTRACT:
A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines, with one line of the pair forming the source region and one line of the pair forming the drain region of each memory cell of the column. Each memory cell has a floating polysilicon storage gate. One of plural wordlines overlies each row of the memory cells. The portion of the wordline overlying each memory cells forms the control gate of the memory cell. Programming and erase operations occur by Fowler-Nordheim tunneling of electrons through a tunnel oxide layer between the floating gate and the source of the cell.

REFERENCES:
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patent: 5793079 (1998-08-01), Georgescu et al.
patent: 6009014 (1999-12-01), Hollmer et al.
patent: 6108229 (2000-08-01), Shau
patent: 6480419 (2002-11-01), Lee
patent: 6687148 (2004-02-01), Shau

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