Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-09-19
2006-09-19
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S901000
Reexamination Certificate
active
07109558
ABSTRACT:
A power MOS transistor formed of an array of source cells and drain cells on an IC chip substrate has a plurality of substrate contact cells, each formed external to the source cells, having respective substrate potential-setting electrodes to which an externally supplied substrate bias voltage can be applied, enabling the substrate potential to be set independently of the source potential of the transistor. It thereby becomes possible to modify the threshold voltage of the transistor or maintain a constant potential difference between the substrate potential and that of a gate input signal. Since the requirement for a substrate contact region within each source cell is eliminated, and the number of substrate contact cells can be fewer than that of the source cells, the chip area occupied by the transistor can be reduced by comparison with a prior art configuration providing such a substrate potential control capability.
REFERENCES:
patent: 4553084 (1985-11-01), Wrathall
patent: 5355008 (1994-10-01), Moyer et al.
patent: 5412239 (1995-05-01), Williams
patent: 5517046 (1996-05-01), Hsing et al.
patent: 5672894 (1997-09-01), Maeda et al.
patent: 5834814 (1998-11-01), Ito
patent: 5999041 (1999-12-01), Nagata et al.
patent: 6140678 (2000-10-01), Grabowski et al.
patent: 6160289 (2000-12-01), Kwon et al.
patent: 6242787 (2001-06-01), Nakayama et al.
patent: 6396249 (2002-05-01), Itakura et al.
patent: A-H01-227520 (1989-09-01), None
patent: A-H02-309714 (1990-12-01), None
patent: A-H03-82151 (1991-04-01), None
patent: A-UM-H04-032543 (1992-03-01), None
patent: A-H04-167813 (1992-06-01), None
patent: A-H06-077796 (1994-03-01), None
patent: 7-263665 (1995-10-01), None
patent: 8-125176 (1996-05-01), None
patent: 9-64707 (1997-03-01), None
patent: 9-266310 (1997-10-01), None
patent: 10-4180 (1998-01-01), None
patent: A-H10-032475 (1998-02-01), None
patent: A-H11-330451 (1999-11-01), None
patent: 2000-101073 (2000-04-01), None
patent: 2001-148464 (2001-05-01), None
patent: A-2001-168697 (2001-06-01), None
US 2002/0017697 A1 (corres. to JP 10-4180).
U.S.S.N. 09/391,236 (corres. to JP 2000-101073).
Fukuda Yutaka
Miura Shoji
Nakano Takashi
Shiraki Satoshi
Ueda Nobumasa
Denso Corporation
Posz Law Group , PLC
Weiss Howard
LandOfFree
Power MOS transistor having capability for setting substrate... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Power MOS transistor having capability for setting substrate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power MOS transistor having capability for setting substrate... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3570357