Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-07-18
2006-07-18
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07080329
ABSTRACT:
Some embodiments of the invention provide a method of identifying a via between at least two layers of a multi-layer design layout. The method identifies a region within which the via should be located. It then formulates an optimization problem for identifying a location of the via in the region. It then solves the optimization problem to find an optimized location for the via.
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U.S. A
Caldwell Andrew
Teig Steven
Cadence Design Systems Inc.
Dinh Paul
Stattler Johansen & Adeli LLP
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